M88SSTE32882H0 is a 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity for DDR3/DDR3L/DDR3U RDIMM applications. It supports DDR3-800/1066/1333/1600/1866/2133 SDRAMs, 1.5V/1.35V/1.25V VDD operations and quad chip selects.
The device buffers the input address and control signals and redrives two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies.
The device is fully compliant with the JEDEC specification. It also provides some extra features such as register read mechanism (patented) to monitor the status of the device without changing its existing pinout, transparent mode to help check DRAM defects, and frequency change on the fly to save power, etc.