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M88SSTE32882D1 - DDR3 Register Buffer (VDD = 1.5V or 1.35V)

M88SSTE32882D1 is a 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 configurable registering clock driver with parity for 1.5V or 1.35V VDD operation. The device is fully compliant with the JEDEC standard. It supports DDR3-800/1066/1333 DRAMs and provides quad chip selects.

M88SSTE32882D1 accepts 28 bits or 26 bits of address and control signals and outputs two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The device provides an extra register read mechanism (patented) beyond the JEDEC spec to enable the status monitoring of the device without changing its existing pinout.


FeatureApplication

Fully compliant with JEDEC SSTE32882 standard

28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registered buffer for address and control signals

DDR3-800/1066/1333 DRAMs support

Quad chip selects support

Dual VDD voltage support: 1.5 V / 1.35 V

Register read operation support (patented)

S3 low power mode support

1T/3T MRS timing support

Pre-launch feature support

Integrated PLL clock driver distributing one differential clock pair to four differential pairs

Constant propagation delay with VT variations

1.5 V/1.35 V CMOS compatible clock and data inputs

1.5 V/1.35 V CMOS outputs

Parity checking on command and address data inputs

Output characteristics configurable through control registers

Different power saving modes support

3.5 mW power consumption in CK Stop mode

Green package: 176-ball TFBGA

High-performance DDR3 RDIMMs

Next-generation computer platform

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