M88SSTE32882D1 is a 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 configurable registering clock driver with parity for 1.5V or 1.35V VDD operation. The device is fully compliant with the JEDEC standard. It supports DDR3-800/1066/1333 DRAMs and provides quad chip selects.
M88SSTE32882D1 accepts 28 bits or 26 bits of address and control signals and outputs two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The device provides an extra register read mechanism (patented) beyond the JEDEC spec to enable the status monitoring of the device without changing its existing pinout.