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Job Description:

Design competitive low power and area-saving analog IP such as PLL, DDR, USB, HDMI, Audio codec, high-speed & high-resolution data coverters(ADC DAC), high speed IO, high-precision-band-gap, LDO, etc.;

Write design spec and conduct feasibility research for advanced IP over above area;

Oversee layout and verification activities including floor plan, LVS and DRC;

Work closely with design validation and characterization team to support successful product release;

Qualification:

3+ years (5+ years for BSEE) of experience in analog design with Bachelor or Master Degree;

Familiar with EDA tools including HSPICE, Spectre, HSIM, Calibre, etc.;

Deep knowledge of analog circuit design such as band-gap, LDO, PLLs, ADC, high-speed ser-des, IO;

Experience in Matlab;

Ability to do layout and provide verification/debugging guidance;

Creative thinker, capable of finding an appropriate solution to complex problems;

Self-driven and proactive;

Team player, able to work in a cross-functional-team environment.


HR Contact: hr@montage-tech.com

Job Description:

Design RF IC for receivers, transmitters and transceivers in Wi-Fi/BT wireless systems;

Design and do layout of IC building blocks, such as LNA, Mixer, PA, TR-Switch, VGA/PGA, Filter and Synthesizer;

Conduct modeling and simulation of devices, circuits and systems in Spectre/SpectreRF, Matlab and EM simulator;

Perform test characterization of IC building blocks and chips in lab, ATE and field environments.

Qualification:

3+ years of experience in RFIC design and MS or PhD in electric and electronic engineering;

Understanding receiver and transmitter architectures for multi-standard wireless systems;

Hands-on design experiences in RF building blocks for System-on-Chips in deep submicron CMOS technologies for mass production;

Proficient with circuit simulators such as Spectre/SpectreRF, oversight of layout design and familiarity with EM simulation;

Demonstrated ability for test characterization of RF building blocks and chip level performances in lab, supporting ATE production and system field tests;

Strong communication skills, self-motivation and also excellence as team player;


HR Contact: hr@montage-tech.com

Job Description:

Module-level RTL implementation based on design specification;

Module-level architecture definition and implementation based on DSP materials (C/C++ or Matlab) ;

Simulation/Verification at both module level and system level;

Chip-level synthesis and timing closing;

Writing design spec and report;

FPGA/silicon debugging on related modules;

Qualification:

Bachelor degree or master degree in ASIC design relevant;

8+ years of experience in digital design;

Solid understanding of state-of-art tape-out flow and methodology from RTL to GDS;

Strong hands-on experience in using widely-adopted EDA tools for netlist generation, formal check and timing fix;

Broad knowledge base and good understanding of timing issues, P&R flow and challenges, DFT, low power design, signal integrity, test and packaging, handling of mixed signal, post-layout ECO, etc.;

Familiar with C/C++, Matlab and some script languages;

Understanding the fundamentals of basic digital signal processing;

Relevant experience in STB, especially in FEC (LDPC/BCH) is better;


HR Contact: hr@montage-tech.com

Job Description:

Module-level architecture definition and design;

Module-level RTL implementation;

Simulation/Verification at both module level and system level;

Module-level synthesis and timing analysis;

Writing design spec and report;

FPGA/silicon debug on related modules.

Qualification:

Bachelor degree or master degree in ASIC design relevant;

5+ years of SoC design experience;

Experience in DDR controller;

Solid knowledge on digital IC design;

Strong skills of Verilog RTL coding and simulation;

Hands-on experience in EDA tools, such as Cadence and Synopsys tools;

Familiar with C language;

Relevant experience in STB product;

Good communication skills and good oral/written English;


HR Contact: hr@montage-tech.com

Job Description:

Develop video/image/audio post-processing algorithm;

Build c model for algorithm and cooperate with HW/SW team for implementation;

Adjust the picture quality performance of our product;

Lead algorithm team to support the SoC project;

Develop display related firmware.

Qualification:

MS/PHD (fresh graduate) in ASIC Design Relevant;

Minimum 1 year of experience in multimedia SoC design;

Experience in some of related fields: de-interlacing, scaling, video/picture enhancement, de-noising, audio post-process, rate conversion, filter design, graphics processing;

Solid theoretical background in digital signal processing;

Excellent programming skills in C/C++ and MatLab;

Relevant experiences in STB product, familiar with HDL (VHDL / Verilog HDL) and video codec standard (mpeg2/mpeg4/H.264/AVS/vc1/vp8/HEVC) is a big plus;

Good communication skills and good oral/written English.


HR Contact: hr@montage-tech.com

Job Description:

Design and develop multi-format video decoder firmware on embedded system;

Work with ASIC design team for the video system performance and function validation including firmware/hardware co-simulation, FPGA verification, etc.;

Co-work closely with software team to improve the framework of firmware, define and implement the API function and customize generic firmware to specific products;

Analyze and fix bugs, and support customer-specific issues.

Qualification:

Master degree with 3+ years of experience or bachelor degree with 5+ years of experience in related field;

Strong C/C++ programming experience is required;

Strong knowledge of video codec, such as MPEG2, H.264, HEVC/H.265, etc.;

Knowledge of Multimedia APIs such as OpenMAX;

Experience in developing multimedia driver (in a certain platform such as Linux, Android, etc.) on popular multimedia platform, such as ffmpeg, Gstreamer, etc.;

Good communication skills and strong team-player mindset;

Experience in video post processing is a plus.


HR Contact: hr@montage-tech.com

Job Description:

Collect function points from design specification, generate/run/debug test cases on FPGA;

Help develop driver for modules and silicon chip bring up, validation and debug;

Perform porting ASIC to FPGA and generate bit file, including simulation, synthesis and P&R;

Build up and maintain FPGA test platforms.

Qualification:

BSEE with 2+ years of working experience in FPGA verification;

Knowledge of digital TV, digital video broadcast system, set-top box, MPEG decoder, TV display and audio system;

Proficient in C programming under Windows or embedded RTOS;

Experience in digital and analog circuit design and debug;

Familiar with lab equipment, such as oscilloscope, logic analyzer, spectrum analyzer, etc.;

Knowledge of PLD/FPGA design flow using Verilog/VHDL and EDA tools such as Xilinx ISE, Altera Quartus.


HR Contact: hr@montage-tech.com

Job Description:

Module-level architecture definition and design;

Module-level RTL implementation;

Simulation/Verification at both module and system level;

Module-level synthesis and timing analysis;

Writing design spec and report;

FPGA/silicon debug on related modules.

Qualification:

Bachelor degree or master degree in ASIC design relevant;

Minimum 5 years of SoC design experience;

Knowledge of video processing;

Solid knowledge in digital IC design;

Strong skills of Verilog RTL coding and simulation

Hands-on experiences in EDA tools, such as Cadence and Synopsys tools;

Familiar with C language;

Relevant experiences in STB product;

Good communication skills and good oral/written English.


HR Contact: hr@montage-tech.com

Job Description:

Generate sub-module design specification from prototype architecture;

Design high-speed (>500MHz) circuit, including RTL coding, IP using, simulation, timing closure and bit file generation;

Perform porting ASIC to FPGA, generate/run/debug test cases on FPGA;

Write Design report;

Build up and maintain FPGA test platforms, including PCB schematic design and layout support.

Qualification:

BSEE with 2 years of experience in circuit design with FPGA;

More experience in IP using/debugging, such as PLL, MCU, PCIe and DDR4 interface;

Knowledge in DDR4 memory system and Intel server platform;

Familiar with lab equipment, such as oscilloscope and logic analyzer;

Familiar with PLD/FPGA design flow using Verilog and EDA tools such as Xilinx ISE and Altera Quartus;

Knowledge in TPM, encryption IP etc. is a plus.


HR Contact: hr@montage-tech.com

Job Description:

Work on PCIE and DDR function verification and performance test;

Do HSDIMM validation and test together with design team;

Develop and merge the auto-test for PCIE and DDR interface in server/bench;

Analyze bug of our product and failure of customer return.

Qualification:

BSEE with minimum 2 years of experience in high-speed interface test;

Familiar with PCI/PCIE/USB validation test or other high-speed interface;

Experience in IC debug or system level failure analysis;

Experience in C language, familiar with python programming is a plus;

Familiar with lab equipments, such as oscilloscope, logic analyzer, BERT, etc.;

Knowledge of PCIE or USB spec, etc.;

Good communication skill, team work spirit, self-motivated;

Quick learner.


HR Contact: hr@montage-tech.com

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