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Job Description:

Design and develop multi-format video decoder firmware on embedded system;

Work with ASIC design team for the video system performance and function validation including firmware/hardware co-simulation, FPGA verification, etc;

Co-work closely with software team to improve the framework of firmware, define and implement the API function and customize generic firmware to specific products;

Analyze and fix bugs, and support customer-specific issues.

Qualification:

Master degree with 3+ years of experience or bachelor degree with 5+ years of experience in related field;

Strong C/C++ programming experience is required;

Strong knowledge of video codec, such as MPEG2, H.264, HEVC/H.265, etc;

Knowledge of Multimedia APIs such as OpenMAX;

Experience in developing multimedia driver (in a certain platform such as Linux, Android, etc.) on popular multimedia platform, such as ffmpeg, Gstreamer, etc;

Good communication skills and strong team-player mindset;

Experience in video post processing is a plus.


HR Contact: hr@montage-tech.com

Job Description:

Module-level architecture definition and design;

Module-level RTL implementation;

Simulation/Verification at both module level and system level;

Module-level synthesis and timing analysis;

Writing design spec and report;

FPGA/silicon debug on related modules.

Qualification:

Bachelor degree or Master degree in ASIC design relevant;

Minimum 5 years of SoC design experience;

Experience in AXI/AHB bus structure and arbiter;

Solid knowledge in digital IC design;

Strong skills of Verilog RTL coding and simulation;

Hands-on experiences in EDA tools, such as Cadence and Synopsys tools;

Familiar with C language;

Relevant experience in set-top box products;

Good communication skills and good oral/written English.


HR Contact: hr@montage-tech.com

Job Description:

Module-level architecture definition and design;

Module-level RTL implementation;

Simulation/Verification at both module and system level;

Module-level synthesis and timing analysis;

Writing design spec and report;

FPGA/silicon debug on related modules.

Qualification:

Bachelor degree or Master degree in ASIC design relevant;

Minimum 5 years of SoC design experience;

Knowledge of video processing;

Solid knowledge in digital IC design;

Strong skills of Verilog RTL coding and simulation;

Hands-on experiences on EDA tools, such as Cadence and Synopsys tools;

Familiar with C language;

Relevant experience in set-top box products;

Good communication skills and good oral/written English.


HR Contact: hr@montage-tech.com

Job Description:

Collect function points from design specification, generate/run/debug test cases on FPGA;

Build up and maintain FPGA test platforms;

Port ASIC to FPGA and generate bit file, including simulation, synthesis and PaR;

Help to develop driver for modules and silicon chip bringing up, validation and debugging.

Qualification:

BSEE,More than 5 years of working experience in FPGA verification;

Knowledge of Digital TV, Digital Video Broadcast system, set-top box, MPEG decoder, TV display and audio system;

Proficient in C programming under Windows or embedded RTOS;

Experience in digital and analog circuit design and debug;

Familiar with lab equipment, such as oscilloscope, logic analyzer, spectrum analyzer, etc;

Knowledge of PLD/FPGA design flow using Verilog/VHDL and EDA tools such as Xilinx ISE, Altera Quartus.


HR Contact: hr@montage-tech.com

Job Description:

Be responsible for the development of the verification platform (SIM/EMU) including the scripts developing, SoC testbench building, evaluating the cutting edge of verification methodology and integrating them into the platform;

Be responsible for the SoC database management, SoC simulation bring up, regression and coverage collection and analysis;

Implement the SoC functional verification tasks from verification plan definition to tests development on both sim and emu platform;

Implement the gate level simulation, low power simulation with UPF;

Qualification:

Bachelor degree in Electrical Engineering or related area, MSEE is preferred;

Minimum 2 years of experiences in ASIC/complex SoC verification;

Strong skills of scripting languages (Python/Makefile/Perl) and hands-on experience of SoC simulation ENV development;

Familiar with HDL languages (Verilog/VHDL/SV), simulation tool-chain (IES/VCS/Questa) and testbench design with SV;

Familiar with assemble instruction sets and know how to integrate low level driver software into SoC architecture;

Solid debugging ability on ARM processors is preferred;

Experience in SoC design with embedded processor and their integration with other system components including memory subsystems and peripherals;

Good communication skills to work closely with IP/SoC/CAD team;

Hands-on experience in UVM is a plus;

Experience in low power verification with UPF/CPF flow is a plus;

Experience in gate level simulation is preferred.


HR Contact: hr@montage-tech.com

Job Description:

Lead PCIe3.0/4.0 PHY development including architecture selection trade-off, design partitioning, circuit and logic design, verification, validation and DFT;

Work with project design team for whole chip integration and verification;

Supervise physical design and conduct SI and PI analysis and optimization;

Work with test engineer to develop engineering and production test platform.

Qualification:

Master degree or 10+ years of experience in high speed IC development and specialized in PCIex PHY;

Deep understanding of PCIex standard and application environments;

Hands on experience in PHY architecture and module design, good insight in the implementation issues, test and debug process;

Familiar with PCIex compliance test;

Proven track record of PCIex PHY product tape out in 28nm process or more advanced process;

Positive mindset, self-driven and good team player;

Good documentation and presentation skill.


HR Contact: hr@montage-tech.com

Job Description:

Work with TM to define new products for enterprise server and data center applications;

Write the architecture and performance requirement spec from the MRD/FRD;

Conduct technical feasibility analysis, identify design challenges and estimate effort;

Work with project leader to define design strategy and execution planning;

Support application engineers for system test and validation.

Qualification:

Master or Ph.D. degree with 10+ years of experience in server CPU development with specialty in system memory control and management;

Proven track record of server CPU development tape out in 20nm or more advanced process nodes;

Solid technical background and in-depth knowledge in CPU architectures and operations;

Excellent written and oral communication skills in both Chinese and English;


HR Contact: hr@montage-tech.com

Job Description:

Micro-architecture definition/writing IC design spec;

RTL coding for logic modules;

Simulation/Verification of functionalities at both module level and top level;

Module level synthesis / timing analysis;

Writing complete design/verification reports;

Silicon debug of the related module functionalities;

Writing test patterns for production tests.

Qualification:

MSEE with 5-6 years of experience in digital design;

Relevant experience in high-speed and low-power digital design is a must;

Solid knowledge of digital design building blocks (Data-path, Synchronizer, FIFO, etc.);

Strong skills of Verilog RTL coding, verification and debug;

Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc;

Relevant experience in DDR interface, flash design is a plus;

Self-motivated and team player.


HR Contact: hr@montage-tech.com

Job Description:

Make Micro-architecture Definition/write IC Design Spec;

Write RTL coding for block or top level;

Do IP level synthesis/timing analysis/formality check/CDC check/Code coverage check;

Assist Verification Engineer to complete module and top level simulation and verification;

Debug RTL/Gate Level waveform at module or top level;

Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.

Qualification:

MSEE with 5-6 years of experience in digital design;

Relevant experience in high speed IO IP design and PCIe design is a plus;

Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;

Hands-on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;

Strong skills of Script and familiar with TCL, Perl, etc.;

Self-motivated, good team work spirit and good communication skills.


HR Contact: hr@montage-tech.com

Job Description:

Participate/Lead ASIC digital verification for various IP/SoC projects;

Create verification plans with designers;

Develop DV architecture and verification environment;

Verification execution and sign-off.

Qualification:

Excellent team working style;

Solid IP/SoC verification background;

Mass production for verified IP/SoC;

Bachelor in EE or CS with at least 7 years of working experience in ASIC digital verification; or Master in EE or CS with at least 5 years of working experience in ASIC digital verification;

Production experience in verification strategies and test plans and in-circuit emulation solution;

Production experience in simulation acceleration solution;

Familiar with x86 architecture, especially on PCI Express;

Familiar with any RISC architecture (ARM, MIPS, etc)

Familiar with system modeling;

Proficiency in System Verilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;

Production experience in ARM buses, such as AXI/AMBA/APB;

Good understanding of modern operating systems and virtualization;

Expert level knowledge of verification tools;

Familiar with Linux, csh/Python or any script languages;

Good English skills (read and write);


HR Contact: hr@montage-tech.com

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