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Job Description:

Lead PCIe3.0/4.0 PHY development including architecture selection trade-off, design partitioning, circuit and logic design, verification, validation and DFT;

Work with project design team for whole chip integration and verification;

Supervise physical design and conduct SI and PI analysis and optimization;

Work with test engineer to develop engineering and production test platform.

Qualification:

Master degree or 10+ years of experience in high speed IC development and specialized in PCIex PHY;

Deep understanding of PCIex standard and application environments;

Hands on experience in PHY architecture and module design, good insight in the implementation issues, test and debug process;

Familiar with PCIex compliance test;

Proven track record of PCIex PHY product tape out in 28nm process or more advanced process;

Positive mindset, self-driven and good team player;

Good documentation and presentation skill.


HR Contact: hr@montage-tech.com

Job Description:

Work with TM to define new products for enterprise server and data center applications;

Write the architecture and performance requirement spec from the MRD/PRD;

Conduct technical feasibility analysis, identify design challenges and estimate effort;

Work with project leader to define design strategy and execution planning;

Support application engineers for system test and validation.

Qualification:

Master or Ph.D. degree with 10+ years of experience in server CPU development with specialty in system memory control and management;

Proven track record of server CPU development tape out in 20nm or more advanced process nodes;

Solid technical background and in-depth knowledge in CPU architectures and operations;

Excellent written and oral communication skills in both Chinese and English;


HR Contact: hr@montage-tech.com

Job Description:

Participate ASIC digital verification for various PCIe IP/SoC projects;

Create PCIe verification plans with designers;

Develop DV architecture and verification environment;

Verification execution and sign-off.

Qualification:

Excellent team work style;

Production experience in PCIe Gen 3 products;

Solid IP/SoC verification background;

Mass production for verified IP/SoC;

Bachelor with 7+ years of experience in ASIC digital verification (Master with 5+ years );

Expert in System Verilog/UVM;

Expert in scripting;

Good English skills (read and write);

Skills plus:

Production experience in simulation acceleration solution;Production experience in in-circuit emulation solution;Familiar with x86 architecture;Good understanding on modern Operating systems and virtualization for PCIe.
HR Contact: hr@montage-tech.com

Job Description:

Development of next generation solutions for advanced memory interfaces of data centers;

High speed SI simulation and analysis;

Extraction of channel model using standard industry tools;

Lab measurements of interconnect channel in frequency and time domains.

Qualification:

MS in Electrical Engineering/Microwave/Physics/Computer Science/Math;

Knowledge of Electromagnetic and Microwave concepts;

Knowledge of a programming or scripting language in a Windows/UNIX environment;

Strong analytical and problem-solving skills;

Passion for technology;

Eager, quick learner with strong team-work spirit;

Excellent technical communication skills.


HR Contact: hr@montage-tech.com

Job Description:

Write micro-architecture definition and design implementation Spec;

Write RTL coding for block or top level;

Do IP level synthesis/timing analysis/formality check/CDC check/Code coverage check;

Assist verification engineers to complete module and top level simulation and verification;

Debug RTL/Gate Level waveform at module or top level;

Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.

Qualification:

MSEE with 5-6 years of experience in digital design;

Relevant experience in high speed IO IP design, and PCIe design experience is a big plus;

Very Strong skills in Verilog RTL coding, simulation debug and base or metal layer ECO;

Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;

Strong skills in Script and be familiar with TCL, Perl, etc.;

Self-motivated, good team work spirit and good communication skills.


HR Contact: hr@montage-tech.com

Job Description:

Design, simulate and verify high speed CMOS analog and mixed-signal circuits;

Work closely with layout designer for layout implementation;

Define specifications of sub-modules and create design documentation;

Do silicon test, characterization and debugging.

Qualification:

MSEE with 1-3 years of experience in analog design;

Solid knowledge and experience in analog and mixed-signal circuit design;

Experience in high speed I/O related area (Transmitter, Receiver, DDR IO interface, etc.) is a plus;

Good understanding of deep submicron CMOS technology process and device physics;

Tape-out experience in 40nm, 28nm is a plus;

Proficiency of EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc.);

Experiences in Verilog, Verilog-A and/or Matlab.


HR Contact: hr@montage-tech.com

Job Description:

Design, simulate and verify high speed CMOS analog and mixed-signal circuits;

Conduct high speed serial link system behavioral modeling;

Supervise layout floor plan and design of IC blocks;

Help define specifications of IC blocks and create design documentation;

Do silicon test, characterization and debugging.

Make knowledge sharing/presentation within design team.

Qualification:

MSEE or above with minimum 7 years of working experience;

Strong experience in DFE (Decision Feedback Equalizer) or CDR (Clock Data Recovery) circuit design;

Experience in DDR or other high speed designs (e.g. PCIe, HDMI, SerDes) is preferred;

Good system level knowledge on high speed serial link;

Strong lab experience in silicon debugging, good understanding on lab instruments (e.g. oscilloscope, network analyzer);

Ability to supervise layout floor plan and design;

Good understanding on deep submicron CMOS technology process and device physics;

Proficiency of EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc.);

Experiences in Verilog, Verilog-A and/or Matlab;

Good communication skill and good command of written English are highly desired.


HR Contact: hr@montage-tech.com

Job Description:

Participate ASIC digital verification for various IP/SoC projects;

Create verification plans with designers;

Develop DV architecture and verification environment;

Do verification execution and sign-off.

Qualification:

Excellent team work style;

Solid IP/SoC verification background;

Mass production for verified IP/SoC;

Minimum 3 years of working experience in ASIC digital verification;

Production experience in verification strategies and test plans;

Familiar with System Verilog/UVM for test bench creation, debug, reuse, constrained-random stimulus and functional coverage;

Production experience in ARM buses, such as AXI/AMBA/APB;

Familiar with verification tools;

Familiar with Linux, csh/Python or other script languages;

Good English reading and writing skills.


HR Contact: hr@montage-tech.com

Job Description:

Support RD Linux/UNIX network/OS/hardware;

Provide Perl/SKILLl/TCL script support and develop necessary scripts or tools for IC designers;

Support EDA tool and EDA design flow, especially digital front end flow (DC/PT/FM/DFT/Incisive/VCS/Conformal/Tessent etc.);

Support timing characterization flow for stand cell/IO/memory/analog IP;

Qualification:

BSEE or MSEE with minimum 1 year of experience;

Familiar with EDA design flow for mixed-signal design;

Familiar with UNIX/Linux Operating system, VNC, Exceed;

Familiar with Computer languages such as C, C++, Perl/TCL/C-shell;

Familiar with version control tools like DesignSync, CVS, SVN, etc.;

LSF or SGE experience is a plus;

Good communication skills.


HR Contact: hr@montage-tech.com

Job Description:

Play a critical role in meeting corporate goals with your experience to develop ATE test hardware & software to support IC design center;

Develop/convert/migrate hardware & software between test systems to increase test coverage and production throughput;

study device specification and use simulation tool to generate test vectors based on device behavior model;

Enhance the existing test techniques for maximum test quality to minimize customer returns and to reduce test time;

Customize existing test hardware to PCBs for test repeatability, cost effectiveness, maintenance and productive debugging;

Procure essential instruments to continuously upgrade test engineering lab for bench-to-tester correlation;

Develop software tools to reduce test program development cycle time by automating generation of test programs from libraries of proven test methods;

Setup/transfer new products and technology for production off-load at off-shore.

Qualification:

Knowledge of ATE testing is essential;

Familiar with Verilog and experience in functional simulation with EDA tool for test vector generation;

Working experience in fast pace semi-conductor manufacturing environment;

Good sense of responsibility and positive working attitude;

Willing to travel at short notice;

BSEE/MSEE in Electronics/Electrical Engineering;

Minimum 2 to 5 years of working experience in semiconductor industry;

Experience in mixed signals and RF testing is preferred;

Good written and oral communication skills;

Knowledgeable of Credence Duo/Teradyne J750, A5 or Catalyst/Agilent AG9300 ATE systems;

Able to understand, debug, modify and improve test programs;

Able to manage sub-contractors at different locations;

Circuit Design (IC) background will be taken as an additional qualification.


HR Contact: hr@montage-tech.com

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