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M88DS3103(B) - DVB-S2/S Demodulator

The M88DS3103(B) is an advanced single-chip demodulator for digital satellite television broadcasting system. It is fully compliant with the DVB-S2/S standard and can support QPSK, 8PSK, 16APSK and 32APSK demodulation schemes. The chip provides a fast, easy-to-apply and cost-effective solution for digital satellite receiver front-end design.

The M88DS3103(B) accepts baseband differential or single-ended I and Q signals from a tuner, then digitizes, demodulates and decodes the signals, and finally outputs an MPEG transport stream. The M88DS3103 supports symbol rates from 1 Msps to 45 Msps, and code rates from 1/4 to 9/10. Its features cover blind scan, fade detection, timing and carrier recovery, performance monitoring, co-channel interference cancellation, command interface, and DiSEqC™ 2.X interface, etc. The device is controlled via a serial 2-wire bus.

The M88DS3103(B) works properly with 1.2 V and 3.3 V voltage supplies. It is available in a 48-pin QFN package and is RoHS compliant.

FeatureApplication

Multi-standard demodulation

Compliant with DVB-S2/S specifications

QPSK, 8PSK, 16APSK and 32APSK demodulation schemes

Maximum channel bit rate: 168 Mbps

Maximum symbol rates: 45 Msps for QPSK, 8PSK and 16APSK; 37 Msps for 32APSK

DSP features

Symbol rate sweeping
I/Q impairment cancellation
Automatic spectrum inversion
Adaptive equalizer for RF reflection removal
Roll-off factor automatic identification
Fast blind scan
High performance on-chip micro-controller
Multi-error monitor
Accurate SNR estimation
Multi-lock indicators
Clipping rate reporter
DC removal
Automatic frequency correction
Fast timing loop acquisition
Robust frame synchronization scheme
Phase noise indicator
Fast system recovery from fading or other abnormal conditions
Co-channel interference cancellation
PID filter

Interface

DVB-S2/S common, parallel and serial MPEG output interfaces compliant
Serial 2-wire bus to configure the device
2-wire bus repeater for tuner configuration
FSK interface
DiSEqC™ 2.X compliant interface, DiSEqC™ envelop mode
General purpose input/output (GPIO)
Dedicated reference clock generation

System

On-chip 8-bit ADC
On-chip PLL for system clock generation from an external 4/8/10/16/27 MHz clock or quartz crystal
Sleep mode supported

Technology

Power supplies: 1.2 V and 3.3 V
Low power consumption
Green package: 48-pin QFN with exposed pad

Digital satellite set-top boxes

Digital satellite receivers

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